The present invention is directed to processes for fabricating MOS devices with ultrathin oxide layers, and particularly to EEPROM fabrication methods and structures.
Electrically Erasable Programmable Read Only Memories (EEPROMs) are nonvolatile memory devices that employ floating gates to store bits of data in individual cells. At each memory cell location, an ultrathin oxide layer called the "tunnel oxide" separates a floating gate from an underlying substrate. To program a memory cell, a voltage exceeding the normal operating voltage is applied to a control gate, which is capacitively coupled to the floating gate, to cause electrons to tunnel from the substrate through the tunnel oxide onto the floating gate in accordance with the well known Fowler-Nordheim principle. Electron tunneling occurs in the presence of a very high electric field applied to the tunnel oxide. Because the tunnel oxide is very thin and experiences such a high electric field, its dielectric integrity is an important design consideration.
An example of an early EEPROM memory cell is described in U.S. Pat. No. 4,203,158, in which a stacked-gate arrangement is employed to facilitate fabrication of a high density integrated circuit (IC) memory. Two layers of polycrystalline silicon ("polysilicon") are used to fabricate the stacked gates. In each memory cell, a first-level polysilicon layer defines the floating gate and a second-level polysilicon layer defines the control gate. An equivalent circuit for one such memory cell is shown in FIG. 1 herein, and is indicated generally by reference numeral 10.
The memory cell 10 of FIG. 1 communicates its stored bit of data to the outside world through a column bit line 12. A series connection of a select transistor 14 and a floating-gate transistor 16 is provided between the bit line 12 and a voltage source or ground line 18. The drain D of select transistor 14 is connected to the bit line 12. The source S of transistor 14 is connected to the drain D of floating-gate transistor 16. The source S of transistor 16 is connected to the source line 18. Transistor 14 has its gate 20 controlled by a row select or "word" line 22. Transistor 16 includes a floating gate 24 and a control gate 26. A program select line 28 is connected to the control gate 26.
To store a first binary logic level in the cell 10, a high programming voltage (e.g.; +20 volts) is applied to the word line 22 and to the program line 28, while the bit line 12 and source line 18 are held at ground. By virtue of capacitive coupling, a sufficiently high voltage appears on the floating gate 24 to cause electrons to tunnel from the drain D of transistor 16 to the floating gate 24, putting it in a negatively charged state. This causes transistor 16 to have a threshold voltage that is high enough to keep it off during a read operation. To store a second binary logic level in the memory cell 10, the program line 28 is grounded while the high programming voltage is applied to the bit line 12 and to the word line 22 with the source line 18 left floating. This causes electrons to tunnel from the floating gate 24 to the drain D of transistor 16, discharging the floating gate 24 and perhaps leaving it with a slight net positive charge. In this state, transistor 16 will have a threshold voltage such that it will be on during a read operation. As those skilled in the art will appreciate, reading is accomplished by applying a normal operating voltage (e.g., +5 volts) to the word line 22 and to the program line 28, then detecting whether transistor 16 is on or off.
EEPROM memories can be manufactured as discrete integrated circuit devices or as components of more complex integrated circuit devices. When the EEPROM memory is included as a relatively small part of a more complex integrated circuit device, the allocation of chip area for each individual memory cell is not as critical as for high-density discrete EEPROMs. Therefore, when the EEPROM is part of a more complex integrated circuit device, it can be laid out using a single polysilicon layer rather than the stacked two-layer arrangement of the aforementioned patent. The slight additional area devoted to such a single-layer implementation does not appreciably effect the size of the integrated circuit device since its other circuitry occupies most of the chip area. The simplification of the fabrication process by resorting to single-layer polysilicon technology more than compensates for the slight additional chip area occupied by the EEPROM portion of the device.
A prior art layout for one EEPROM memory cell using single-layer polysilicon technology is illustrated in FIG. 2, wherein the memory cell is indicated generally by reference numeral 100. A cross section through a portion of the memory cell 100 is illustrated in FIG. 3. The cross section is taken through a floating-gate transistor 102 and a tunneling capacitor 104. FIG. 4 is an enlarged view of a portion of FIG. 3 at one edge of the tunneling capacitor 104.
With particular reference to FIG. 3, the device is fabricated on a P(--) substrate 106. One of many active areas of the device is shown defined within a thick field oxide 108, typically formed by a conventional LOCOS (local oxidation of silicon) process. The active area is selectively doped with N-type impurities to create transistor regions and a capacitor plate. In particular, a relatively deep N-type region 110 defines a lower capacitor plate of the tunneling capacitor 104. The junction depth of region 110 is typically 0.4 microns. An adjoining N-type region 112 at an intermediate depth (e.g., about 0.2 microns) defines the drain of floating-gate transistor 102. Another intermediate depth N-type region 114 defines the source of floating-gate transistor 102. Shallow N-type extensions 116 are formed by conventional lightly doped drain ("LDD") processing, and define the channel 118 of transistor 102 therebetween. The floating-gate transistor 102 has a structure above the substrate 106 that includes a thin gate oxide 120, a gate 122 and sidewall oxide spacers 124. Similarly, the tunneling capacitor 104 has a structure above the substrate 106 that includes an ultrathin tunnel oxide 126, an upper capacitor plate 128, and sidewall oxide spacers 130. Overlying and passivating the entire structure is a composite reflowed glass layer 132, typically having an undoped SiO.sub.2 lower portion and a doped SiO.sub.2 upper portion (which are not separately delineated in the drawing).
Referring specifically to FIG. 4, the upper capacitor plate 128 includes a lower N-type polysilicon layer 134 and an upper tantalum silicide (TaSi.sub.2) layer 136. The TaSi.sub.2 layer is formed by a conventional deposition technique, and is provided in order to increase the conductivity of the conductive lines used in the device. The gates of the various transistors of the integrated circuit device have the same tantalum silicide/polysilicon structure. Silicides using refractory metals other than tantalum are known in titanium, moly bedinum and tungsten. The art, including, e.g., the use of a silicide of a refractory metal atop a polysilicon layer is hereinafter referred to as "silicided polysilicon". The thicknesses of the various layers are not drawn to scale but generally depict the shapes and positions of the elements of the structure. The tunnel oxide 126 is ultrathin, typically being only about 65 .ANG. to 70 .ANG. thick. The silicided polysilicon layer 128 is typically about 3500 .ANG. thick, with its component layers 134 and 136 being about 2000 .ANG. and 1500 .ANG. thick respectively. The thickness of glass layer 132 is typically about 8000 .ANG..
Referring again to FIG. 2, a first silicided polysilicon layer includes a relatively large rectangular portion 140 and narrow fingers 142 and 144, which extend from the large portion 140. The relatively large rectangular portion 140 overlies an active area 146 that is entirely doped N-type. The doped active area 146 serves as the program line for the memory cell 100 and similar memory cells (not shown) in the same row. The portion of program line 146 below the large rectangular portion 140 of the first silicided polysilicon layer serves as a control gate of the floating-gate transistor 102. The finger 142 defines the floating gate of floating-gate transistor 102. The finger 144 defines the upper capacitor plate of the tunneling capacitor 104. It will be appreciated that silicided polysilicon portion 140 and the underlying portion of program line 146 together with the oxide layer therebetween define a biasing capacitor 148 that is connected in series with the tunneling capacitor 104 to enable a voltage to be applied to the tunneling capacitor sufficient to cause electron tunneling during programming of the memory cell 100.
Another active area 150 includes three separate N-type doped regions 152, 154 and 156. The locations of the N-type regions in FIG. 2 are indicated by the shading. Region 152 corresponds to source region 114 and the adjoining LDD region 116 of FIG. 3. Region 154 corresponds to capacitor plate region 110, drain region 112 and the adjoining LDD region 116 of FIG. 3.
With further reference to FIG. 2, a second silicided polysilicon layer 158 overlies N-type region 152 and defines a select transistor 160 where it crosses active area 150 between N-type regions 154 and 156. The polysilicon layer 158 defines a word line for a row of memory cells. A first metal line 162, which is shown broken away, runs through the memory cell 100 and similar memory cells (not shown) in the same column to provide a voltage source to the column of memory cells. Metal line 162 is normally at ground potential but can be disconnected from ground when required during programming. Connection between the metal source line 162 and an extension 164 of N-type region 152 is made at a contact site 166. A second metal line 168, which is also shown broken away, runs through the memory cell 100 and similar memory cells in the same column, and serves as a bit line for such column of memory cells. Connection between the metal bit line 168 and the N-type region 156 is made at contact site 170.
FIG. 5 illustrates a circuit diagram for the memory cell 100 with the circuit elements and conductive lines arranged in approximately the same locations as for the physical layout of FIG. 2, using the same reference numerals where applicable to designate the corresponding parts. The circuit operates by charging and discharging the floating gate 142 to program the logic state of the memory cell 100 in a manner similar to the operation of the memory cell 10 of FIG. 1.
Referring to FIGS. 2 and 5, a relatively high programming voltage (in this case about +14 volts) is applied to word line 158 and program line 146, while bit line 168 and source line 162 are held at ground. Approximately 2/3 of the high programming voltage appears by capacitive coupling across the tunneling capacitor 104, causing electrons to tunnel from its lower plate (i.e., region 154) to its upper plate (i.e., the finger 144). Of course, this causes the entire silicided polysilicon layer 140/142/144 to become negatively charged so that floating-gate transistor 102 will stay off during a read operation. To reverse the charge on the tunneling capacitor 104, the program line 146 is grounded while the high programming voltage is applied to the bit line 168 and to the word line 158 with the source line 162 left floating. Reading is accomplished by applying a normal operating voltage (e.g., +5 volts) to the word line 158 (to turn on transistor 160) and to the program line 146, then detecting whether transistor 102 is on or off by conventional sensing circuitry (not shown) at one end of the bit line 168.
Referring again to FIG. 4, it will be appreciated that the ultrathin tunnel oxide 126 experiences a very high electric field in the programming mode. Only about 70 .ANG. of oxide are used to support about 10 volts in either direction. With almost 10 volts on the upper capacitor plate 128, electrons will tunnel through oxide layer 126 from the lower capacitor plate 110, which is held at ground potential. The high electric field needed for programming threatens to cause dielectric breakdown through the tunnel oxide 126 at its weakest point. The dashed line 176 at the edge of the tunnel oxide 126 may be vulnerable to dielectric breakdown and a short circuit failure at that point. The dashed line 176 represents the interface between thermally grown oxide layer 126 and a deposited oxide layer that is used to form the sidewall oxide spacer 130. Furthermore, the lower pointed corner 178 of the upper capacitor plate 128 gives rise to a high electric field concentration at that point. This high electric field concentration occurs precisely where the dielectric integrity of the oxide is vulnerable, i.e., at the interface 176.
The coincidence of the vulnerable interface 176 and the pointed corner 178 occurs due to the conventional processing steps employed. Referring again to FIGS. 2 and 3, the field oxide 108 is formed to define the active areas. This is followed by a moderate dose N-type ion implantation using a conventional mask to selectively dope the active area 146 entirely, as well as the portions of the active area 150 at the site of the tunneling capacitor 104 (i.e., forming region 110 in FIG. 3) and a portion of region 152 where the word line 158 will lie across it when subsequently formed. Then the oxide layer that will subsequently define the gate oxide of transistors 102 and 160 is grown in the active areas 146 and 150 to a thickness of about 250 .ANG.. In active area 146 this oxide layer will form the dielectric of the biasing capacitor 148, which is defined by the large rectangular silicided polysilicon portion 140 and the underlying portion of active area 146.
At this point, the tunnel oxide 126 is formed. It has been the practice to etch out a rectangular opening as indicated by the dashed box 180 in FIG. 2 using a conventional photoresist mask. Then, after the etch step and photoresist removal, a thermal oxide layer is grown to a thickness of about 65 .ANG. to 70 .ANG. in the area within the box 180. During such oxidation step, the gate oxide of transistors 102 and 160 and dielectric oxide of biasing capacitor 148 increase in thickness to about 260 .ANG., i.e., about four times the tunnel oxide thickness, which is a factor in determining the relative capacitances of the biasing capacitor 148 and the tunneling capacitor 104.
A sequence of conventional processing steps follows in which the aforementioned silicided polysilicon layers are formed. The fabrication continues with LDD ion implantation, sidewall oxide formation, and source/drain ion implantation. Referring to FIG. 4, the delineation of the silicided polysilicon pattern includes an anisotropic etch that produces both the pointed corner 178 of the polysilicon layer 134 and the vertical edge 176 of the tunnel oxide layer 126. It will be appreciated that the interface 176 between oxide layers 126 and 130 is relatively vulnerable to dielectric breakdown.
It has been understood for two decades that undercut gates caused by isotropic etching (i.e., "wet etching") techniques could be filled in at the site of the undercut to improve dielectric integrity by resorting to a reoxidation step at an intermediate stage of the process. This technique is described in U.S. Pat. No. 4,553,314, which was highly successful in eliminating gate-shorting problems caused by undercut gates. However, as process technology evolved, reoxidation became less critical in importance and in some cases became impractical. As anisotropic etching (or "dry etching") techniques were introduced into standard fabrication processes, gate undercutting was substantially eliminated as a source of yield and reliability problems. The further introduction of various metal silicide formation techniques provided an impediment to use of reoxidation. Process irregularities can occur when the silicon in the silicide layer reacts with oxygen at the high temperatures used in conventional thermal oxidation procedures.
Due to such problems, reoxidation has been difficult to implement in processes that employ metal silicide/polysilicon layers. The use of the refractory metals tantalum, titanium, molybedinum and tungsten in making metal silicides is known in the art. See, e.g., U.S. Pat. No. 4,505,027. Tantalum disilicide (TaSi.sub.2) is a common metal silicide used together with an underlying polysilicon layer to fabricate gate structures in conventional complementary metal-oxide-semiconductor (CMOS) devices. See, e.g., U.S. Pat. No. 4,640,844. In order to successfully implement reoxidation following tantalum silicide layer formation, silicon in excess of the tantalum disilicide stoichiometry must be provided in the silicide layer. See U.S. Pat. No. 4,505,027, Column 4, lines 49-54.
Experiments have shown that the process requires extremely tight control of Si to Ta ratio in the composition of the tantalum silicide layer. It has been found that the Si to Ta ratio must be maintained in the range from 2.45 to 2.50. The tantalum silicide layer is a composition of TaSi.sub.2 and elemental Si microcrystals. When the ratio of Si to Ta is maintained below 2.45, the reoxidation step will cause silicon from the polysilicon layer to be pulled up into the tantalum silicide layer as available silicon in the tantalum silicon layer reacts to form SiO.sub.2. This causes a "ditching" phenomenon at random locations in the polysilicon layer, resulting in certain transistors exhibiting increased threshold voltages to the point of being operationally nonfunctional. When the ratio of Si to Ta is maintained above 2.50, the reoxidation step causes nodules or "whiskers" of primarily silicon to extrude out of the tantalum silicide, in some cases contacting the substrate surface and creating a short circuit. However, by maintaining the Si to Ta ratio in the extremely tight range of from 2.45 to 2.50 and by holding the reoxidation step to a very short duration, it is possible to obtain functional devices. Nonetheless, the tight tolerances required are difficult to implement consistently so that acceptable yields can be achieved.